1. Field of the Invention
This invention relates to a digital-to-analog conversion system with a compensation circuit (hereinbelow, called "DAC system") in which the linearity error of a digital-to-analog converter (hereinbelow, called "DAC") of inferior linearity characteristics is compensated for by the use of the compensation circuit. More particularly, it relates to a DAC system which has a construction suitable for the form of an IC by employing a ramp voltage generator for the reference of the compensation of the linearity of a DAC output.
2. Description of the Prior Art
Regarding the compensation of the linearity error of a DAC, a circuit arrangement shown in FIG. 1 has been known. Hereunder, a method of compensation in the circuit arrangement of FIG. 1 will be described.
In a conventional DAC, the linearity of a DAC output corresponding to an upper bit of a digital input signal (hereinafter, it shall be simply termed "linearity", and the linearity error of the DAC output based thereon shall be referred to as "linearity error") is inferior, and the linearity of a lower bit of the digital input signal is good as compared with that of the upper bit. It is therefore possible to compensate for the linearity error of the upper bit by utilizing the lower bit.
In FIG. 1, by way of example a case is supposed where a digital input signal 10 is made up of an upper bit part 10a including 4 bits and a lower bit part 10b including 6 bits, totaling 10 bits, and where the linearity of the upper 4 bits is inferior while the linearity of the lower 6 bits is superior. It is also assumed that the linearity error of the upper 4 bits is expressed by at most lower 6 bits (.+-.1/2LSB.times.32) including the sign bit, with a unit of 1/2 LSB.
The digital input signal 10 is applied through a register 11 to a first DAC 12, in which it is converted into an analog current I.sub.o. This current I.sub.o is converted into a voltage E.sub.o by means of an output amplifier 13 which consists of an operational amplifier 13-1 and a feedback resistor 13-2. The voltage E.sub.o is converted into a digital quantity 10' of 10 bits by an analog-to-digital converter (hereinafter, termed "ADC") of high precision.14. In an adder 15, the digital quantity difference 15a between the digital quantity 10' and the digital input signal 10 is calculated. The digital quantity difference 15a is a quantity corresponding to a linearity error for the upper bits of the digital input signal, and can be expressed by 5-6 bits or so with the sign bit included. It is written into that address of a memory 16 which has been appointed by the address signal 10a composed of the upper 4 bits of the digital input signal 10.
The above processings are executed for all the 2.sup.4 signals (0000, 0001, 0010, . . . 1111) constituting the upper 4 bits of the digital input signal, and linearity errors for the respective signals are successively written into predetermined addresses of the memory 16.
In a digital-to-analog converting operation for any digital input signal 10 made up of 10 bits, the digital input signal 10 is fed through the resister 11 and is converted into the current I.sub.o by the first DAC 12. Using the upper 4 bits of the digital input signal 10 as an address, a corresponding linearity error is read out as a compensation quantity from the memory 16. The read compensation quantity is fed through a register 17 and is converted into a current I.sub.o ' by a second DAC 18. This current I.sub.o ' is added to the current I.sub.o.
The current value (I.sub.o +I.sub.o ') obtained by the addition is converted into a voltage value by the output amplifier 13. Thus, the output voltage E.sub.o with the error of the upper 4 bits of the digital input signal compensated for is obtained.
Accordingly, when a compensation circuit portion 19 in FIG. 1 is assembled in the DAC of poor linearity characteristics into the form of a 1-chip IC, an integrated DAC system of high precision ought to be obtained.
With the circuit arrangement of FIG. 1, however, even when a successive approximation type ADC or an integration type ADC commercially available is used as the ADC 14, the DAC system is unsuited to the form of an IC because of the complicated circuit arrangement of the ADC. Another disadvantage is that, since the ADC 14 needs to be operated for all the 2.sup.4 signals constituting the upper 4 bits of the input signal, the period of time for obtaining the linearity errors becomes long.